1. Statement of the Technical Field
The inventive arrangements relate to digital communication equipment using an error correction technique. More particularly, the inventive arrangements relate to a serially concatenated convolutional code decoder.
2. Description of the Related Art
A serially concatenated convolutional code (SCCC) decoder provides a means for recovering information bits from a codeword. A codeword is often comprised of a bitstream that has been encoded using a forward error correction (FEC) technique based on at least one convolutional code. A codeword may be a relatively large sequence of information bits (for example, a few thousand information bits) to provide a high recoverability of encoded information contained therein.
One algorithm that is conventionally used in SCCC decoders for decoding coded sequences is the MAP algorithm. MAP is an acronym for the phrase “Maximum Aposteriori Probability.” The MAP algorithm provides a method for determining the most probable information bits which were transmitted based on a noisy signal received over a communication channel. It is known in the art that the MAP algorithm is an inherently Soft-Input, Soft-Output (SISO) algorithm. Soft information refers to soft-values (which are represented by soft-decision bits) that comprise information about the bits contained in a coded sequence. In particular, soft-values are values that represent the probability that a particular bit in a coded sequence is either a one (1) or a zero (0). For example, a soft-decision value for a particular bit can indicate that a probability of a bit being a one (1) is p(1)=0.3. Conversely, the same bit can have a probability of being a zero (0) which is p(0)=0.7. The most commonly used soft values are log-likelihood ratios (LLR's). An LLR which is a positive value suggests that the bit is most likely to be a one (1) whereas a negative LLR suggests that the value of the bit is most likely a zero (0).
It is known that soft values can be used in SCCC devices for decoding concatenated codes. In general, concatenated codes use two codes (an inner code and an outer code) with some interleaving between them. Accordingly, SCCC decoders are commonly implemented with two separate decoders that are each utilizing MAP algorithms for the decoding process. An inner decoder decodes the inner code and an outer decoder decodes the outer code. The decoders are commonly configured for operation in an iterative process where the outputs of one decoder is repeatedly communicated to the other decoder. Since the MAP algorithm is a SISO type algorithm, the soft-values (represented by soft decision bits) generated by the MAP algorithm in one decoder can be used as inputs to the MAP algorithm in the other decoder.
During a first iteration of a concatenated code, an inner decoder processes soft-decision value approximations to bits output from an inner encoder. As a result of this processing, the inner decoder outputs soft-decision value approximations to the bits that were input to the inner encoder in an encoding process. Similarly, the outer decoder uses soft-decision value approximations to bits output from an outer encoder. Since the bits output from the outer encoder were permuted or interleaved (as explained in the preceding paragraph), the soft-decision value approximations are derived by applying a reverse permutation to the soft-decision value approximations output from the inner decoder prior to being communicated to the outer decoder. This reverse permutation is known in the art as depermutation. The outer decoder can produce two different outputs. One is a soft-decision value approximation to data that was input to the outer encoder. This data is the original, unencoded data, and is not of interest until a final iteration. This data need not be permuted or depermuted. The other output of the outer decoder is a refinement to soft-decision value approximations to bits output from an outer encoder. This output is interleaved (i.e., re-arranged) in the same manner as an encoder permuted output bits of the outer encoder prior to communicating the bits to the inner encoder. These permuted soft-decision value approximation outputs from the outer decoder approximate the bits input to the inner encoder and can therefore be used in a second iteration of the decoding process.
During the second iteration of the decoding process, the permuted soft-decision value approximation outputs are communicated to the inner decoder. In this regard, it should be appreciated that the inner decoder uses the permuted soft-decision values approximations of bits input to the inner encoder to produce refined soft-decision value approximations of bits input to the inner encoder. The inner decoder also uses the soft-decision value approximations of bits output from the inner encoder to produce refined soft-decision value approximations of bits input to the inner encoder.
A plurality of SCCC decoders can be implemented in a parallel configuration on a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). Each of the SCCC decoders is coupled to a respective random access memory (RAM) data store via a system bus. Each RAM data store contains data needed by a respective SCCC decoder to sequentially write sets of serially linked soft-decision bits to a depermutation and/or a permutation buffer memory for storage. Each RAM data store also contains data needed by a respective SCCC decoder to non-sequentially read sets of serially linked soft-decision bits from the depermutation and/or permutation buffer memory.
Each SCCC decoder is comprised of an input buffer memory, a processing loop module, and an output buffer memory. The input buffer memory is comprised of hardware and firmware configured to receive encoded soft-decision bits from an external device and to temporarily store the same. The processing loop module is comprised of hardware and firmware configured to decode soft-decision bits using an iterative process (described in greater detail below). In this regard, it should be appreciated that the processing loop module is often comprised of an inner decoder module, a depermutation module, an outer decoder module, and a permutation module. The output buffer memory is comprised of hardware and firmware configured to receive decoded soft-decision bits from the processing loop module and to temporarily store the same.
With regard to the processing loop module, the burden of decoding information contained within a codeword is split between the inner decoder module and the outer decoder module. In this regard, it should be appreciated that the inner decoder module and the outer decoder module employ methods of maximum a posteriori (MAP) decoding or max-log approximations to MAP decoding. MAP decoding and max-log approximations to MAP decoding are well known to persons skilled in the art. Thus, such methods will not be described in great detail herein.
The inner decoder module is often comprised of hardware and firmware configured to obtain a sequence of soft-decision bits from the input buffer memory and/or the permutation module. Upon receipt of all or a portion of a soft-decision bit sequence, the inner decoder module begins processing the received soft-decision bits. This processing typically involves performing a relatively simple decoding operation based on a corresponding convolutional inner code. After processing the soft-decision bits, the inner decoder communicates the processed soft-decision bits to the depermutation module for depermutation (i.e., rearrangement or reorganization) and storage in a depermutation buffer memory. In this regard, if should be understood that the depermutation of processed soft-decision bits is accomplished by reading the stored soft-decision bits from the depermutation buffer memory in an order different from an order in which the soft-decision bits were written to the depermutation buffer memory for storage. It should also be understood that depermutation of soft-decision bits is necessary to reverse a permutation of information bits that occurred in an encoding process.
The outer decoder module is comprised of hardware and firmware configured to receive a sequence of depermuted soft-decision bits communicated from the depermutation module. Upon receipt of all or a portion of a soft-decision bit sequence, the outer decoder module begins processing the received soft-decision bits. This processing typically involves performing a relatively simple decoding operation based on a corresponding conventional outer code. After processing the soft-decision bits, the outer decoder module communicates the processed soft-decision bits to the permutation module for permutation (i.e., rearrangement or reorganization) and storage in a permutation buffer memory. It should be understood that permutation is necessary to realign the soft-decision bits to the permutation that occurred in an encoding process. The permutation of processed soft-decision bits is accomplished by reading the stored soft-decision bits from the permutation buffer memory in an order different from an order in which the soft-decision bits were written to the permutation buffer memory for storage. Thereafter, a sequence of permuted soft-decision bits is communicated, along with the original codeword, to the inner decoder module.
The above described process is performed for ‘M’ iterations. After ‘M’ iterations, the outer decoder module produces decoded information bits. Subsequently, the outer decoder module forwards the decoded information bits to the output buffer memory for storage.
Despite the advantages of such a conventional SCCC decoder, it suffers from certain drawbacks. For example, the above-described decoding system employing a number of parallel processing SCCC decoders and associated RAM data stores is hardware resource intensive. Furthermore, the above described decoding process requires a relatively large amount of time to complete. As such, there also remains a need for a SCCC decoder having an improved processing time with a negligible performance loss.